By Bart Vermeulen, Kees Goossens (auth.)
This e-book describes an technique and assisting infrastructure to facilitate debugging the silicon implementation of a System-on-Chip (SOC), permitting its linked product to be brought into the marketplace extra speedy. Readers research step by step the main necessities for debugging a latest, silicon SOC implementation, 9 components that complicate this debugging job, and a brand new debug procedure that addresses those necessities and complicating elements. The authors’ novel communication-centric, scan-based, abstraction-based, run/stop-based (CSAR) debug method is mentioned intimately, displaying the way it is helping to satisfy debug specifications and deal with the 9, formerly pointed out components that complicate debugging silicon implementations of SOCs. The authors additionally derive the debug infrastructure specifications to help debugging of a silicon implementation of an SOC with their CSAR debug process. This debug infrastructure involves a known on-chip debug structure, a configurable computerized design-for-debug move for use in the course of the layout of an SOC, and customizable off-chip debugger software program. assurance comprises an overview of the potency and effectiveness of the CSAR technique and its assisting infrastructure, utilizing six commercial SOCs and an illustrative, instance SOC version. The authors additionally quantify the expense and layout attempt to help their approach.